Government takes steps to train 85,000 chip designers in 315 institutions

NEW DELHI: The government said the Chips to Startups (C2S) programme under India Semiconductor Mission has made progress towards its target of training 85,000 engineers in semiconductor design over ten years, with students in 315 academic institutions currently participating in chip design training.

Union electronics and IT minister Ashwini Vaishnaw said world-class Electronic Design Automation (EDA) tools supported by companies such as Synopsys, Cadence, Siemens, Renesas, Ansys and AMD have been made available to these institutions to enable hands-on training in chip design.

Students are gaining experience in semiconductor design, fabrication, packaging and testing. The chips designed by students are fabricated and tested at the Semiconductor Laboratory (SCL) in Mohali, allowing exposure to the full semiconductor development cycle.

As per the ministry, the programme has recorded more than 1.85 crore hours of EDA tool usage so far for chip design training.




Students from institutions across the country, from Assam to Gujarat and from Kashmir to Kanyakumari, are participating in semiconductor design activities through the initiative.

Vaishnaw said the semiconductor industry is expected to expand from $800-900 billion currently to $2 trillion in the coming years, creating demand for nearly two million skilled professionals globally.

He said the programme will be expanded under India Semiconductor Mission 2.0, increasing coverage from the current 315 institutions to 500 academic institutions.

The expansion aims to widen access to semiconductor training and strengthen the talent pipeline for chip design, fabrication, packaging and testing across the country.

The govt said the programme is part of broader efforts under the India Semiconductor Mission to build domestic capability in the semiconductor sector through training, infrastructure and industry partnerships.
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